UGPCB 로고
소개: Industrial Significance and Technical Challenges of Via Filling
~ 안에 2023, the global PCB market surpassed $89.3 10억 (Prismark), with via filling technology critically influencing over 30% yield fluctuations in 5G communication devices. This article analyzes thermodynamic equations and process matrices to reveal how via filling impacts signal integrity and thermal reliability.
1. Via Filling Technology Framework
1.1 Microvia Physics and Process Window
Per IPC-6012E, vias are defined as conductive holes ≤0.70mm (28밀). The filling process window follows:
D = (K×T)/(σ×η)
Where:
- 디: Maximum fillable diameter (mm)
- 티: Substrate Tg (℃)
- σ: Resin surface tension (mN/m)
- 또는: Filler viscosity (Pa·s)
- 케이: Process coefficient (0.02–0.05)
For FR-4 substrates (Tg=140°C), filling holes >0.40mm requires 재료 with σ<25mN/m and η<120Pa·s.
2. Resin Filling Physics
2.1 Buried Via Depth Threshold
Resin filling becomes mandatory for buried vias ≥0.8mm due to laminating flow dynamics:
P = (γ×cosθ)/(r×h)
Where:
- 피: Filling pressure (MPA)
- γ: Prepreg surface tension
- θ: Contact angle
- r: Via radius
- h: Via depth
At h≥0.8mm, standard lamination pressure (3–5MPa) fails to fill voids, necessitating vacuum-assisted resin filling.
2.2 Resin vs. Lamination Filling: 6-Dimensional Comparison
| Parameter | 수지 충전 | Lamination Filling |
|---|---|---|
| Thickness Uniformity | ± 5% | ±15% |
| Delamination Risk | <0.1% | 0.5–1.2% |
| 비용 | $0.35/dm² | $0.12/dm² |
| 최소 트레이스 너비 | 50μm | 75μm |
| Thermal Cycles | 3,000 | 1,500 |
| Signal Loss (@10GHz) | 0.15dB/inch | 0.25dB/inch |
3. Solder Mask Filling Process
3.1 Ink Flow Model in Negative Imaging
Solder mask filling follows a modified Hagen-Poiseuille equation:
Q = (πr⁴ΔP)/(8μL) × (1 – e^(-t/τ))
With time constant τ=μr²/(4γ), explaining 50% fill rates in semi-filled vias when exposure time t≈τ.
3.2 HASL Board Failure Case Study
Unfilled vias in 5G base station PCBs caused tin beads, modeled by the Arrhenius equation:
t_f = A×exp(Ea/(kT))
Testing showed MTBF dropped from 10 에게 2.3 years at 85°C/85%RH. Implementing 0.30mm vias with solder mask openings ≤(via diameter +0.08mm) reduced tin bead defects from 12% 에게 0.7%.
4. Advanced Via Filling Technologies
4.1 Conductive Filling for EMI Shielding
Silver epoxy filling enhances shielding effectiveness (SE):
SE = 20log(1/(1-아르 자형)) + 10log(N)
~에 80% fill rate (ρ=0.8), SE improves by 18dB at 1GHz.
4.2 Plated Copper Filling for Signal Integrity
Copper-filled via impedance:
Z0 = (87/√ε_r)ln(5.98h/(0.8w+t))
Copper pillars reduce impedance variation from ±15% to ±5%, lowering BER from 10⁻⁶ to 10⁻¹² at 28Gbps.
5. Process Decision Framework
Total Cost of Ownership (TCO) Analysis
- 가전제품: Solder mask filling offers lowest 5-year TCO
- 자동차: 수지 + partial copper filling ensures reliability
- 군대: Copper pillars optimize signal integrity
결론
Via Filling for 6G Applications
As terahertz frequencies demand sub-50μm via precision, nano-silver sintering emerges as a breakthrough. Mastering via filling physics will drive next-gen 고주파 PCB 혁신.
